AMD smartNICs to meld ASICs, FPGAs, Arm cores
"It doesn't matter if one particular heterogeneous component is solving the function or a combination of heterogeneous functions. From a software perspective, it should just look like one SoC," he said.
For customers who want to add functions that won't change frequently,"you can also completely hot add or remove new accelerator functions in the programmable logic." Specifically, the smartNIC features 16 A78-AE cores for high-performance workloads and four R52 cores for low-power and lights-out operations.Finally, networking and host communication will be provided by a pair of 200Gbps interfaces and 16 lanes of PCIe 5.0 or CXL 2.0 connectivity.AMD anticipates numerous use cases for its smartNICs, including offloading common virtualization tasks like Open vSwitch and Virtio.
"Virtio Net is very popular because it allows you to paravirtualize… the network adapter for VMs. We support two models for Virtio Net. One is bare metal Virtio, where the entire control plane and data plane are consumed by the smartNIC SoC… we also support the BBVA model, where the data path is in the adaptive smartNIC SoC, but the control plane can remain on the host."
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